Microprocessors and other instruction execution devices are known that employ variable length instruction sets, such as Intel® X86 family of microprocessors. Also, processors are known that execute different instruction sets, such as a variable length instruction set (e.g., X86 type instructions) and other instruction sets such as fixed length RISC instruction sets. With multi-instruction set processors, variable length instructions are sometimes converted to a plurality of fixed length native instructions to speed up execution of the variable length instruction. For example, an X86 based processor, may use a plurality of RISC instructions that may be fixed length instructions, to represent one or more variable length instructions. Typically, the RISC instructions are executed out of an onboard memory and are user accessible. An arithmetic logic unit, for example, may then receive the RISC instructions and execute the RISC instructions at a more efficient rate. Accordingly, integer instructions and other instructions may be converted from a non-native instruction to one or more native instructions.
However, a problem can arise when variable length instructions, such as normative instructions, require the setting of flags in various flag registers for particular instructions. For example, if a set of variable length instruction are emulated using a plurality of fixed length native instructions and the fixed length native instructions update the flag registers that are used by other non-native instructions, the updating of the flags in the various flag registers during emulation can corrupt the state used by instructions being executed for other arithmetic logic units or other processor elements relying on the other variable length instructions being executed that also rely on the flag settings. One method of solving such a problem may be to save and restore flag states, but this can result in excessive overhead requirements.
Consequently, there exists a need for a method and apparatus for processing program instructions in a multi-instruction set processing device, that helps suitably control the preservation of flag settings for variable length instructions that are emulated using fixed length native instructions.